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features ? supply voltage up to 40v operating voltage v s = 5v to 18v slew rate control accordin g to lin specification 2.0 supply current during sleep mode typically 10 a supply current in silent mode typically 40 a linear low-drop voltage regulator: ? normal mode: v cc = 5v 2%/50 ma ? silent mode: v cc = 5v 7%/50 ma ?sleep mode: v cc is switched off v cc undervoltage detection (10 ms rese t time) and watchdog reset logically combined at output nres possibility of boosting the voltage regul ator with an exte rnal npn transistor lin physical layer accordin g to lin specification 2.0 wake-up capability via lin bus or wake pin wake-up recognition txd time-out timer 60v load dump prot ection at lin pin bus pin is overtemperature and short circuit protected versus gnd and battery adjustable watchdog time via external resistor positive and negative trigger input for watchdog 5v cmos compatible i/o pins to mcu analog temperature monitor output high emc and esd level package: qfn 5 5 with 20 pins 1. description the ata6621 is a fully integrated lin transceiver, complying with the lin specifica- tion, and with a low-drop voltage regulator for 5v/50 ma output and a window watchdog adjustable via an external resistor. in this qfn20 package, the voltage reg- ulator is able to source 50 ma at v s = 18v even at an ambient temperature of 105c. the output current of the regulator can be boosted by using an external npn transis- tor. this combination makes it possible to develop simple, but powerful and cheap, slave nodes in lin bus systems. ata6621 is designed to handle the low speed data communication in vehicles, for example, in convenience electronics. improved slope control at the lin driver ensures secure data communication up to 20 kbaud. the bus output is capable of withstanding 60v. sleep mode and silent mode guarantee a very low current consumption. lin transceiver with 5v regulator and watchdog ata6621 rev. 4887b?auto?01/06
2 4887b?auto?01/06 ata6621 figure 1-1. block diagram 16 v cc v cc v s adjustable watchdog oscillator short circuit and overtemperature protection txd time-out timer debounce time internal testing unit control unit slew rate control wake-up bus timer standby mode undervoltage reset normal mode 5v 2%/50 ma silent mode 5v 7%/50 ma filter watchdog out 14 1 5 17 11 rxd gnd gnd ntrig ptrig tm mode temp en txd wake receiver 9 4 15 13 3 2 v cc v cc normal mode 18 19 12 7 20 lin wd_osc nres pvcc vcc vs
3 4887b?auto?01/06 ata6621 2. pin configuration figure 2-1. pinning qfn20 67 8 10 9 20 19 18 mlp 5 mm 5 mm 0.65 mm pitch 20 lead ata6621 16 11 12 13 14 15 txd nres wd_osc tm mode gnd temp pvcc vcc vs nc rxd nc lin nc gnd wake ntrig ptrig en 5 4 3 2 1 17 table 2-1. pin description pin symbol function 1 en enables the device into normal mode 2 ptrig high-level watchdog trigger input from microcontroller; if not needed, leave open or connect to gnd 3 ntrig low-level watchdog trigger input from microcontr oller; if not needed, leave open or connect to vcc 4 wake high-voltage input for local wake-up request; if not needed, connect to vs 5 gnd system ground 6 nc not connected 7 lin lin bus line input/output 8 nc not connected 9 rxd receive data output 10 nc not connected 11 txd transmit data input; active low output (strong pull down) after a local wake-up request 12 nres output undervoltage and watchdog reset 13 wd_osc watchdog oscillator 14 tm for factory testing only (tie to ground) 15 mode for factory testing only (tie to ground) 16 gnd additional ground 17 temp chip temperature output pin 18 pvcc 5v regulator sense input pin 19 vcc 5v regulator output/driver pin 20 vs battery supply backside heat slug is connected to gnd (pin 5)
4 4887b?auto?01/06 ata6621 3. functional description 3.1 supply pin (vs) the lin operating voltage is v s = 5v to 18v. an undervoltage detection is implemented to dis- able transmission if v s falls below 5v in order to avoid false bus messages. after switching on vs, the ic starts with the pre normal mode and the voltage regulator is switched on (that is, 5v/50 ma output capability). the supply current in sleep mode is typically 10 a, and 40 a in silent mode. 3.2 ground pin (gnd) the ic is neutral on the lin pin in case of gnd disconnection; it can handle a ground shift up to 3v for supply voltage at the vs pin above 9v. 3.3 voltage regulator output pin (vcc) the internal 5v voltage regulator is capable of driving loads with up to 50 ma of current con- sumption; it is able to supply the microcontroller and other ics on the pcb. it is protected against overloads by means of current limitation and overtemperature shutdown. furthermore, the output voltage is monitored and will cause a reset signal at th e nres output pin if the output voltage drops below a defined threshold v thun . to boost up the maximum load current, an exter- nal npn transistor may be used with its base connected to the vcc pin and its emitter connected to pvcc. 3.4 voltage regulator sense pin (pvcc) this is the sense input pin of the 5v voltage regulator. for normal applications (that is, when only using the internal output transistor), this pin is connected to the vcc pin. if an external boosting transistor is used, the pvcc pin must be c onnected to the output of this transistor, its emitter terminal. 3.5 bus pin (lin) a low side driver with internal current limita tion and thermal shutdown, and an internal pull-up resistor in compliance with lin specification 2. 0 is implemented. this is a self-adapting current limitation; that is, during current limitation, as the chip temperature increases, the current decreases. the allowed voltage range is between ?40v and +60v. reverse currents from the lin bus to vs are suppressed, even in case of ground shifts or battery disconnection. lin receiver thresholds are compatible to the lin protocol specification. the fall time from recessive bus state to dominant, and the rise time from dominant bus state to recessive are slope controlled. 3.6 input pin (txd) this pin is the microcontroller interface to control the state of the lin output. txd must be pulled to ground in order to have the lin bus low. if txd is high, the lin output transistor is turned off and the bus is in the recessive state, pulled up by the internal resistor.
5 4887b?auto?01/06 ata6621 3.7 txd dominant time-out function the txd input has an internal pull-up resistor. an internal timer prevents the bus line from being driven permanently in the dominant state. if txd is forced to low longer than t dom > 20 ms, the lin bus driver is switched to the recessive state. 3.8 output pin (rxd) this pin reports the state of the lin bus to the microcontroller. lin high (recessive state) is reported by a high level at rxd, lin low (dominant state) is reported by a low level at rxd. the output has an internal pull-up structure with typically 5 k ? to v cc . the ac characteristics can be defined with an external load capacitor of 20 pf. the output is short-circuit protected. in unpowered mode (that is, v s = 0v), rxd is switched off. 3.9 enable input pin (en) this pin controls the operation mode of the interfac e. if en is high, the interface is in normal mode, with transmission paths from txd to lin and from lin to rxd both being active. the v cc voltage regulator is ope rating with 5v 2%/50 ma output capability. if en is switched to lo w while txd is still high, the device is forced to silent mode. no data trans- mission is then possible and the current consumption is reduced to i vs = 50 a. the current capability of the v cc regulator is also 50 ma, but the v cc tolerance is between 4.65v and 5.35v. if en is switched to low while txd is low, the device is forced to sleep mode. no data transmis- sion is possible and the voltage regulator is switched off. 3.10 wake input pin (wake) this pin is a high voltage input used to wake the device up from sleep mode. it is usually con- nected to an external switch in the applicati on to generate a local wake-up. a pull-up current source with typically 10 a is implemented. if you don?t need a local wake-u p in your application, connec t pin wake directly to pin vs. 3.11 mode and tm input pins these inputs are used for a special test mode of the watchdog in final production measurement at atmel. in the application, they are always connected to gnd. wake-up events from sleep mode: lin bus wake pin en pin
6 4887b?auto?01/06 ata6621 3.12 modes of operation figure 3-1. modes of operation 3.12.1 normal mode this is the normal transmitting and receiving mode. the voltage regulator is in normal mode and can source 50 ma. the undervoltage detection is activated. the watchdog needs a trigger signal from ptrig or ntrig to avoid resets at nres. 3.12.2 silent mode a falling edge at en while txd is high switches th e ic into silent mode. the txd signal has to be logic high during the mode select window ( figure 3-2 on page 7 ). for en and txd either two independent outputs can be used, or two outputs from the same microcontroller port; in the sec- ond case, the mode change is only one command. in silent mode, the transmission path is disabled. supply current from v bat is typically i vssi = 40 a with no load at the vcc regulator. the overall supply current from v bat is the addition of 40 a plus the v cc regulator output current i vccs . unpowered mode, v bat = 0v pre normal mode vcc: 5v/50 ma with undervoltage reset communication: off go to sleep command local wake-up event local wake-up event go to silent command txd = 0 en = 0 en = 1 en = 1 txd = 1 en = 0 en = 0 b a c + d c + d b b b a: v s > 5v b: v s < 4v c: bus wake-up event d: wake-up from wake-up switch sleep mode vcc: switched off communication: off normal mode vcc: 5v 7%/50 ma with undervoltage reset communication: off normal mode vcc: 5v 2%/50 ma with undervoltage reset communication: on
7 4887b?auto?01/06 ata6621 in silent mode, the 5v regulator is in low tolerance mode (4.65v to 5.35v) and can source up to 50 ma. the internal slave termination between pin lin and pin vs is disabled to minimize the power dissipation in case pin lin is shorted to gnd. only a weak pull- up current (typically 10 a) between pin lin and pin vs is present. the silent mode voltage tolerance is sufficient to run the internal timers of the microcontroller. the undervoltage reset is now v ccths < 4.4v. if an undervoltage c ondition occurs, the nres is switched to low and the ata6621 changes state to pre normal mode. a falling edge at pin lin followe d by a dominant bus level mainta ined for a certain time period (t bus ) results in a remote wake-up request. the device switches from silent mode to pre normal mode. the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at pin rxd to interrupt the microcontroller. ( figure 3-5 on page 10 ) with en high, you can switch directly from silent mode to normal mode. figure 3-2. switch to silent mode delay time sleep mode t d _sleep = maximum 20 s mode select window lin switches directly to recessive mode t d = 3.2 s lin vcc nres txd en sleep mode
8 4887b?auto?01/06 ata6621 figure 3-3. lin wake-up waveform diagram (from silent mode) 3.12.3 sleep mode a falling edge at en while txd is low switches the ic into sleep mode. the txd signal has to be logic low during the mode select window ( figure 3-4 on page 9 ), see section ?silent mode? on page 6 . in sleep mode the transmission path is disabled. supply current from v bat is typically i vssleep = 10 a. the v cc regulator is switched off. nres and rxd are low. the internal slave termination between pin lin and pin vs is disabled to minimize the power dissipation in case pin lin is shorted to gnd. only a weak pull-up current (typically 10 a) between pin lin and pin vs is present. a falling edge at pin lin followe d by a dominant bus level mainta ined for a certain time period (t bus ) results in a remote wake-up request. the device switches from sleep mode to pre normal mode. the vcc regulator is activated and the intern al lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at pin rxd to interrupt the microcon- troller. ( figure 3-5 on page 10 ) with en high you can switch directly from silent mode to normal mode. in the application where the ata6621 supplies the microcontroller, wake-up from sleep mode is only possible via lin or pin wake. regulator wake-up time node in silent mode if undervoltage, switch to prenormal mode undervoltage detection active silent mode 4.5v to 5.5v/50 ma pre normal mode 5v/50 ma normal mode 5v/50 ma low pre normal mode normal mode high en high high nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus
9 4887b?auto?01/06 ata6621 figure 3-4. switch to sleep mode 3.12.4 pre normal mode at system power-up the device automatically switches to pre normal mode. the voltage regula- tor is switched on v cc = 5v 2%/50 ma (see figure 3-6 on page 12 ). the nres output switches to low for t res = 10 ms and sends a reset to the microcontroller. lin communication is switched off and the watchdog is active. the ata6621 stays in this mode until en is switched to high. if v battery (v s < 4v) is powered down during silent mode or sleep mode, the ic powers up into pre normal mode. 3.12.5 unpowered mode if you connect battery voltage to the application circuit, the voltage at the vs pin increases due to the block capacitor ( figure 3-6 on page 12 ). when v s becomes higher than the v s undervolt- age threshold v s_th , the ic mode changes from unpowered mode to pre normal mode. the v cc output voltage reaches its nominal value after t vcc . this time depends on the v cc capacitor and the load. the nres is low for the reset time delay t reset . during this time, no mode change is possible. delay time sleep mode t d _sleep = maximum 20 s mode select window lin switches directly to recessive mode t d = 3.2 s lin vcc nres txd en sleep mode
10 4887b?auto?01/06 ata6621 figure 3-5. lin wake-up waveform diagram from sleep mode table 3-1. table of modes mode of operation transceiver vcc wd_osc temp rxd lin pre normal off 5v 2.5v 2v 5v recessive normal on 5v 2.5v 2v 5v recessive silent off 5v 0v 0v 5v recessive sleep off 0v 0v 0v 0v recessive regulator wake-up time node in silent mode off state on state low pre normal mode normal mode high en high node ln operation microcontroller start-up time delay reset time low or floating low or floating nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus
11 4887b?auto?01/06 ata6621 3.13 wake-up scenarios 3.13.1 remote wake-up via dominant bus state a falling edge at pin lin followe d by a dominant bus level mainta ined for a certain time period (t bus ) results in a remote wake-up request. the device switches to pre normal mode. the v cc voltage regulator is activated, and the internal slave termination resistor is switched on. the remote wake-up request is indicated by a low level at pin rxd to generate an interrupt in the microcontroller. the watchdog needs a trigger sign al from ptrig or ntrig within the lead time t d to avoid resets at nres. ( figure 3-2 on page 7 ) 3.13.2 local wake-up via pin wake a falling edge at pin wake followed by a low level maintained for a certain time period (t wake ) results in a local wake-up request. the extra long wake-up time (t wake ) ensures that no tran- sients as defined in iso7637 create a wake-up. the device switches to pre normal mode. the internal slave termination resistor is switched on. the local wake-up request is indicated by a low level at pin rxd to generate an interrupt in the microcontroller. the watchdog needs a trigger signal from ptrig or ntrig within the lead time t d to avoid resets at nres. 3.13.3 wake-up source recognition the device can distinguis h between a local wake-up request (pin wake) and a remote wake-up request (dominant lin bus state). the wake-up source can be read on pin txd in pre normal mode. if an external pull-up resistor (typically 5 k ? ) on pin txd to the power supply of the micro- controller has been added, a high level indicates a remote wake-up request (weak pull down at pin txd) and a low level indicates a local wake-up request (strong pull down at pin txd). the wake-up request flag (signalled on pin rxd) as well as the wake-up source flag (signalled on pin txd) are reset immediately, if the microcontroller sets pin en to high ( figure 3-2 on page 7 and figure 3-3 on page 8 ). 3.14 fail-safe features during a short circuit at lin, the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff and the lin output is switched off. the chip cools down and after a hysteresis of t hys , switches the output on again. during lin overtemperature switch-off, the v cc regulator works independently. the reverse current at pin lin is very low (< 3 a) during loss of v bat or gnd. this is optimal behavior for bus systems where some slave modes are supplied from battery or ignition. during a short circuit at v cc , the output limits the output current to i vccn . because of undervoltage, nres switches to low and sends a reset to the microcontroller. the ic switches into pre normal mode. if the chip temperature exceeds the value t vccoff , the v cc output switches off. the chip cools down and after a hysteresis of t hys , switches the output on again. because of pre normal mode, the v cc voltage will switch on again although en is switched off from the microcontroller. the microcontroller can start its normal operation. pin en provides a pull-down resistor to force the transceiver into recessive mode if en is disconnected. pin rxd is set floating if v bat is disconnected. pin txd provides a pull-up resistor to force the transceiver into recessive mode if txd is disconnected. if the wd_osc pin has a short circuit to gnd or the resistor is disconnected, the watchdog oscillator runs with a high frequency an d guarantees a reset in any condition.
12 4887b?auto?01/06 ata6621 the wd_osc pin is a constant voltage regulator which supplies 2.5v for the external resistor rosc to adjust the watchdog timing. this output is short circuit protected. a short circuit to gnd causes a reset a pin nres after typically 4 ms. an open circuit causes a reset at pin nres after typically 7 ms. 3.15 voltage regulator the voltage regulator needs an external capacitor for compensation and to smooth the distur- bances from the microcontroller. it is recommend to use an electrolytic capacitor with c > 1.8 f and a tantalum capacitor with c = 100 nf. the values of these capacitors can be varied by the customer, depending on the application. during mode change from silent to normal mode, the voltage regulator ramps up to 6v for only a few microseconds before it drops back to 5v. this behavior depends on the value of the load capacitor. with 4.7 f, the overshoot voltage has its greatest value. this voltage decreases with higher or lower load capacitors. the main power dissipation of the ic is created from the v cc output current i vcc , which is needed for the application. in figure 3-7 on page 13 you see the safe operating range of the ata6621. figure 3-6. vcc voltage regulator: ramp up and undervoltage nres 5v vcc vs t t t 5v v thun t res_f t res t vcc 3v 5.5v 12v
13 4887b?auto?01/06 ata6621 figure 3-7. power dissipation: safe operating area versus v cc output current and supply voltage v s at different ambient temperatures 3.16 watchdog the watchdog anticipates a trigger signal from the microcontroller at the ntrig (negative edge) or the ptrig (positive edge) input within a period time window of t wd . the trigger signal must exceed a minimum time t trigmin > 3 s. if a triggering signal is not received, a reset signal will be generated at output nres. the timing basis of th e watchdog is provided by the internal oscilla- tor, of which the time period t osc is adjustable via the external resistor r wd_osc (10 k ? to 120 k ? ). in silent or sleep mode, the watchdog is sw itched off to reduce current consumption. minimum time for first watchdog pulse is required after the undervoltage reset at nres disap- pears and is defined as lead time t d . 3.16.1 typical timing sequence with r wd_osc = 51 k ? the trigger signal t wd is adjustable between 2.9 ms and 33 ms via the external resistor r wd_osc . for example, with an external resistor of r wd_oscsc = 51 k ? 1%, the typical parameters of the watchdog come out as follows: t osc = 12.5 s due to 51 k ? t d = 3922 12.5 s = 49 ms t 1 = 800 12.5 s = 10 ms t 2 = 840 12.5 s = 10.5 ms t nres = 157 12.5 s = 1.96 ms 0 5 10 15 20 25 30 35 40 45 50 55 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 v s (v) i vcc (ma) t amb = 125?c t amb = 105?c
14 4887b?auto?01/06 ata6621 after ramping up the battery voltage, the 5v regulator is switched on. the reset output nres stays low for the time t reset (typically 10 ms), then it switches to high and the watchdog waits for the watchdog sequence from the microcontroller. this lead time t d follows after the reset and is t d = 49 ms. in this time, the first watchdog pulse from the microcontroller is required. if the trigger pulse ntrig (or ptrig, as the case may be) occurs during this time, the time t 1 starts immedi- ately. if no trigger signal occurs during the time t d , a watchdog reset with t nres = 1.96 ms will reset the microcontroller after t d = 49 ms. the times t 1 and t 2 have a fixed relationship with each other. a triggering signal from the microcontroller is anticipated within the time frame of t 2 = 10.5 ms. to avoid false triggering from glitches, the trigger pulse must be longer than t trigg > 3 s. this slope serves to restart the watch dog sequence. should the triggering signal fail in this open window t 2 , the nres output will be drawn to ground after t 2 . a triggering signal dur- ing the closed window t 1 causes nres to immediately switch low. figure 3-8. timing sequence with r wd_osc = 51 k ? 3.16.2 worst case calculation with r wo_osc = 51 k ? the internal oscillator has a tolerance of 20% . this means that t 1 and t 2 can also vary by 20%. the worst case calculation for the watchdog period t wd the microcontroller has to provide is cal- culated as follows. the ideal watchdog time t wd is between (t 1 maximum) and (t 1 minimum plus t 2 minimum). t 1,min = 0.8 t 1 = 8 ms, t 1,max = 1.2 t 1 = 12 ms t 2,min = 0.8 t 2 = 8.4 ms, t 2,max = 1.2 t 2 = 12.6 ms t wdmax = t 1min + t 2min = 8 ms + 8.4 ms = 16.4 ms t wdmin = t 1max = 12 ms t wd = 14.2 ms 2.2 ms (15%) a microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly within the time period of t wd = 14.2 ms (15%) in an application with r wd_osc = 51 k ? . t nres = 1.9 m s undervoltage reset watchdog reset t reset = 10 ms t 1 = 10 ms t trigg > 3 s t 2 = 10.5 ms t 2 t 1 t wd t d = 49 ms v cc = 5v ptrig ntrig nres
15 4887b?auto?01/06 ata6621 3.17 temperature monitor at pin temp in addition to the internal temperature monitoring of the voltage regulator, an additional sensor measures the junction temperature and provides a linearized voltage at the temp pin. together with the analog functions of the microcontrol ler (for example, the analog comparator and the analog-to-digital converter (adc)), this enabl es the application to detect overload conditions and to take corresponding measures in order to prevent damage. an external capacitor buffers the voltage due to the input current of the adc. the sensor itself is built out of three diodes which are supplied by an internal bias current in pre normal mode and normal mode. the typical voltage at t = 27c is v temp = 2.2v with a typical negative temperature coefficient of v tc,temp = ?5.4 mv/k. figure 3-9. temperature monitor table 3-2. table of watchdog timings rwd_osc k ? oscillator period t osc /s lead time t d /ms closed window t 1 /ms open window t 2 /ms trigger period from microcontroller t wd /ms reset time t nres /ms 10 2.6 10.2 2.08 2.18 2.90 0.41 51 12.5 49.4 10 10.5 14.2 1.96 91 22.4 87.8 17.92 18.82 25.45 3.52 120 29 113.7 23.2 24.36 32.94 4.55 temp 20 a v cc
16 4887b?auto?01/06 ata6621 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min typ max unit v s - continuous supply voltage - transient voltage (load dump) ?0.3 +40 +44 v wake dc and transient voltage (with 33 k ? serial resistor) transient voltage due to iso7637 (coupling 1 nf) ?40 ?150 +40 +100 v logic pins (rxd, txd, en, nres, ptrig, ntrig, pvcc, wd_osc, temp) ?0.3 +6.5 v lin - dc voltage - transient voltage ?40 ?150 +60 +100 v v cc dc voltage ?0.3 6.5 v esd (din en 6100-4-2) according lin emc test specification 1.3 - pin vs, lin to gnd - pin wake (33 k ? serial resistor) 6 5 kv kv esd hbm - all pins according to esd s 5.1 2 kv cdm esd stm 5.3.1-1999 - all pins 1 kv junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c operating ambient temperature t a ?40 +125 c thermal resistance junc tion to heat slug r thjc 10 k/w thermal resistance junction to ambient, where heat slug is soldered to pcb r thja 35 k/w thermal shutdown of v cc regulator 150 165 170 c thermal shutdown of lin output 150 165 170 c thermal shutdown hysteresis 10 c
17 4887b?auto?01/06 ata6621 5. electrical characteristics 5v < v s < 18v, t amb = ?40c to +125c no. parameters test conditions p in symbol min typ max unit type* 1 vs pin 1.1 nominal dc voltage range v s 518va 1.2 supply current in sleep mode sleep mode v lin >v bat ? 0.5v v bat < 14v (25c to 125c) i vssleep 10 20 a a 1.3 supply current in silent mode bus recessive; v bat < 14v (25c to 125c) without load at vcc i vssi 40 55 a a 1.4 supply current in normal mode bus recessive without load at vcc i vsrec 4maa 1.5 supply current in normal mode bus dominant vcc load current 50 ma i vsdom 55 ma a 1.6 vs undervoltage threshold vs th 4.0 4.5 5 v a 1.7 vs undervoltage threshold hysteresis vs th_hys 0.2 v a 2 rxd output pin 2.1 low-level input current normal mode; v lin = 0v v rxd = 0.4v irxd 2 5 8 ma a 2.2 low-level output voltage i rxd = 1 ma vrxdl 0.4 v a 2.3 internal 5 k ? resistor to vcc rrxd 3 7 k ? a 3 txd input pin 3.1 low-level voltage input v txdl ?0.3 +1.5 v a 3.2 high-level voltage input v txdh 3.5 vcc + 0.3v va 3.3 pull-up resistor v txd = 0v r txd 125 250 600 k ? a 3.4 high-level leakage current v txd = 5v i txd ?3 +3 a a 3.5 low-level input current at local wake-up request pre normal mode; v lin = v battery v wake = 0v v txd = 0.4v i txdwake 258maa *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
18 4887b?auto?01/06 ata6621 4en input pin 4.1 low-level voltage input v enl ?0.3 +1.5 v a 4.2 high-level voltage input v enh 3.5 vcc + 0.3v va 4.3 pull-down resistor v en = 5v r en 125 250 600 k ? a 4.4 low-level input current v en = 0v i en ?3 +3 a a 5 nres output pin 5.1 high-level output voltage v s 5.5v; i nres = ?1 ma v nresh 4.2 v a 5.2 low-level output voltage v s 5.5v; i nres = ?1 ma v nresl 0.4 v a 5.3 low-level output low 10 k ? to vcc; v cc = 0.8v v nresll 0.3 v a 5.4 undervoltage reset time v vs 5.5v c nres = 20 pf t reset 713msa 5.5 reset debounce time for falling edge v vs 5.5v c nres = 20 pf t res_f 5sa 6 voltage regulator vcc pin in normal and pre normal mode 6.1 output voltage vcc 5.5v < v s < 18v (0 ma to 50 ma) vcc nor 4.9 5.1 v a 6.2 output voltage vcc at low vs 3.3v < v s < 5.5v vcc low v vs ? v d 5.1 v a 6.3 regulator drop voltage v s > 4.0v, i vcc = ?20 ma v d1 250 mv a 6.4 regulator drop voltage v s > 4.0v, i vcc = ?50 ma v d2 500 mv a 6.5 regulator drop voltage v s > 3.3v, i vcc = ?15 ma v d3 200 mv a 6.6 output current v s > 3v i vcc ?50 ma a 6.7 output current limitation v s > 0v i vccs ?200 ?130 ma a 6.8 load capacity 1 ? < esr < 5 ? c load 1.8 2.2 f d 6.9 vcc undervoltage threshold referred to vcc v s > 5.5v v thunn 4.4 4.8 v a 6.10 hysteresis of undervoltage threshold referred to vcc v s > 5.5v vhys thun 40 mv a 6.11 ramp up time v s > 5.5v to vcc > 4.9v c vcc = 2.2 f r load at vcc: 100 ? t vcc 12msa 7 voltage regulator vcc pin in silent mode 7.1 output voltage vcc 5.5v < v s < 18v (0 ma to 50 ma) vcc nor 4.65 5.35 v a 7.2 output voltage vcc at low vs 3.3v < v s < 5.5v vcc low v vs ? v d 5.1 v a 7.3 regulator drop voltage v s > 3.3v, i vcc = ?15 ma v d 200 mv a 5. electrical characteristics (continued) 5v < v s < 18v, t amb = ?40c to +125c no. parameters test conditions p in symbol min typ max unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
19 4887b?auto?01/06 ata6621 7.4 at vcc undervoltage threshold the state switches back to pre normal mode referred to vcc v s > 5.5 v thuns 3.9 4.4 v a 7.5 hysteresis of undervoltage threshold referred to vcc v s > 5.5v vhys thun 40 mv d 7.6 output current limitation v s > 0v i vccs ?200 ?130 ma a 8 lin bus driver: bus load conditions: load1 (small): 1 nf, 1 k ? ; load2 (large): 10 nf, 500 ? ; rrxd = 5 k ? ; c rxd = 20 pf 10.5, 10.6 and 10.7 specify the timing parameters for proper operation at 20 kbps 8.1 driver recessive output voltage load1 / load2 v busrec 0.9 v s v s va 8.2 driver dominant voltage v vs = 7v r load = 500 ? v _losup 1.2 v a 8.3 driver dominant voltage v vs = 18v r load = 500 ? v _hisup 2va 8.4 driver dominant voltage v busdom_drv_losup v vs = 7v r load = 1000 ? v _losup_1k 0.6 v a 8.5 driver dominant voltage v vs = 18v r load = 1000 ? v _hisup_1k_ 0.8 v a 8.6 pull-up resistor to vs the serial diode is mandatory r lin 20 30 60 k ? a 8.7 self-adapting current limitation v bus = v batt_max t j = 125c t j = 27c t j = ?40c i bus_lim 52 80 120 110 170 230 ma ma ma a 8.8 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus = 0v v battery = 12v i bus_pas_dom ?1 ma a 8.9 leakage current lin recessive driver off 8v < v battery < 18v 8v < v bus < 18v v bus v batt i bus_pas_rec 15 20 a a 8.10 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network gnd device = v s v battery = 12v 0v < v bus < 18v i bus_no_gnd ?10 0.5 10 a a 8.11 node has to sustain the current that can flow under this condition. bus must remain operational under this condition v battery disconnected v sup_device = gnd 0v < v bus < 18v i bus 0.5 3 a a 5. electrical characteristics (continued) 5v < v s < 18v, t amb = ?40c to +125c no. parameters test conditions p in symbol min typ max unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
20 4887b?auto?01/06 ata6621 9 lin bus receiver 9.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec ) / 2 v bus_cnt 0.475 v s 0.5 v s 0.525 ? v s va 9.2 receiver dominant state v en = 5v v busdom ?27 0.4 v s va 9.3 receiver recessive state v en = 5v v busrec 0.6 v s 40 v a 9.4 receiver input hysteresis v hys = v th_rec ? v th_dom v bushys 0.028 v s 0.1 v s 0.175 v s va 9.5 wake detection lin high-level input voltage v linh v s ? 1v v s + 0.3v v a 9.6 wake detection lin low-level input voltage initializes a wake-up signal v linl ?27 v s ? 3.3v v a 10 internal timers 10.1 dominant time for wake- up via lin bus v lin = 0v t bus 30 90 150 s a 10.2 time delay for mode change from pre normal to normal mode via pin en v en = 5v t norm 51520sa 10.3 time delay for mode change from normal into sleep mode via pin en v en = 0v t sleep 2 7 12 s a 10.4 txd dominant time-out timer v txd = 0v t dom 51020msa 10.5 duty cycle 1 th rec(max) = 0.744 v s ; th dom(max) = 0.581 v s ; v s = 7.0v to 18v; t bit = 50 s d1 = t bus_rec(min) / (2 t bit ) d1 0.396 a 10.6 duty cycle 2 th rec(min) = 0.422 vs; th dom(min) = 0.284 vs; v s = 7.0v to 18v; t bit = 50 s d2 = t bus_rec(max) / (2 t bit ) d2 0.581 a 10.7 slope time falling and rising edge at lin slope time dominant and recessive edges t slope_fall t slope_rise 3.5 22.5 s a 10.8 time of low pulse for wake-up via pin wake v wake = 0v t wake 60 130 200 s a 11 internal receiver electrical ac parameters of the li n physical layer lin receiver, rxd load conditions (c rxd ): 20 pf 11.1 propagation delay of receiver ( figure 5-1 on page 22 ) t rec_pd = max(t rx _ pdr , t rx_pdf )t rx_pd 6sa 11.2 symmetry of receiver propagation delay rising edge minus falling edge t rx_sym = t rx_pdr ? t rx_pdf t rx_sym ?2 2 s a 5. electrical characteristics (continued) 5v < v s < 18v, t amb = ?40c to +125c no. parameters test conditions p in symbol min typ max unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
21 4887b?auto?01/06 ata6621 12 watchdog input ptrig and ntrig 12.1 watchdog input high- level threshold v_h ptrig 3.5 v a 12.2 watchdog input low threshold v_l ptrig 1.5 v a 12.3 internal pull down ptrig internal pull down ptrig rpd ptrig rpu ntrig 125 200 k ? a 13 watchdog oscillator 13.1 voltage at wd_osc in normal mode i wd_osc = ?250 a v wd_osc 2.3 2.5 2.7 v a 13.2 possible values of resistor r osc 10 120 k ? a 13.3 oscillator period r osc = 10 k ? t osc 2.1 2.6 3.1 s a 13.4 oscillator period r osc = 51 k ? t osc 10 12.5 15 s a 13.5 oscillator period r osc = 91 k ? t osc 17.9 22.4 26.8 s a 13.6 oscillator period r osc = 120 k ? t osc 23.2 29 34.8 s a 14 watchdog timing relative to t osc 14.1 watchdog lead time after reset t d 3922 cycles a 14.2 watchdog closed window t 1 800 cycles a 14.3 watchdog open window t 2 840 cycles a 14.4 watchdog reset time nres t nres 157 cycles a 15 temperature monitor at pin temp 15.1 voltage at temp in normal mode (t = ?40c) i temp = 3 a v temp 2.35 2.7 v a 15.1 voltage at temp in normal mode (t = 27c) i temp = 3 a v temp 2.0 2.35 v a 15.1 voltage at temp in normal mode (t = 125c) i temp = 3 a v temp 1.4 1.9 v a 15.2 short current at temp vtemp = 0v i temp ?30 ?15 a a 15.3 temperature gradient v tc,temp ?5.4 mv/k c 16 wake pin 16.1 high-level input voltage v wakeh v s ? 1v v s + 0.3v v a 16.2 low-level input voltage initializes a wake-up signal v wakel ?27 v s ? 3.3v v a 16.3 wake pull-up current v s < 27v, v wake = 0v i wake ?30 ?10 a a 16.4 high-level leakage current v s = 27v; v wake = 27v i wakel ?5 +5 a a 5. electrical characteristics (continued) 5v < v s < 18v, t amb = ?40c to +125c no. parameters test conditions p in symbol min typ max unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
22 4887b?auto?01/06 ata6621 figure 5-1. definition of bus timing parameters txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
23 4887b?auto?01/06 ata6621 figure 5-2. application circuit 67 8 10 9 20 19 18 mlp 5 mm 5 mm 0.65 mm pitch 20 lead ata6621 16 11 12 13 14 15 txd nres lin sub bus wd_osc tm mode master node pull-up gnd temp pvcc vcc vs nc rxd nc lin nc gnd wake wake-up switch 10 k ? 1 k ? 33 k ? 10 k ? ntrig ptrig ntrig ptrig microcontroller reset txd rxd en v cc v battery en 5 4 3 2 1 17 220 pf 100 nf 22 f + 100 nf 10 f 1 nf +
24 4887b?auto?01/06 ata6621 figure 5-3. application circuit with external npn 67 8 10 9 20 19 18 mlp 5 mm 5 mm 0.65 mm pitch 20 lead ata6621 16 11 12 13 14 15 txd nres lin sub bus wd_osc tm mode master node pull-up gnd temp pvcc vcc vs nc rxd nc lin nc gnd wake wake-up switch 10 k ? 1 k ? 33 k ? 10 k ? 3 ? ntrig ptrig ntrig ptrig microcontroller reset txd rxd en v cc v battery en 5 4 3 2 1 17 + 220 pf 100 nf mjd31c 100 f 2.2 f + 100 nf 10 f 1 nf +
25 4887b?auto?01/06 ata6621 7. package information 6. ordering information extended type number package remarks ATA6621-PGQW qfn20 pb-free
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